Opticore team proposed (PRX 9, 2019) and demonstrated (Nat. Photonics 17, 723–730) the first photonic logic based on photoelectric multiplication in coherent detection, which is the fundamental building block to enable large-scale, low energy computing with O(N) devices for O(N2) computes per clock cycle. As photonic technologies have become a necessity in datacenters for chip-to-chip communications, computing in the optical domain is an ultimate solution to overcome the electronic bottlenecks in energy efficiency and computing density with minimum change to the existing data center infrastructure.
The “memory wall” in AI computing stems from the capacitive resistance of metallic wires used for memory data movement, which limit clock speeds (1-3 GS/s) and lead to energy consumption. Opticore OPUs utilize the same high-bandwidth memories (HBMs) for their scalability and performance, but here the OPUs convert memory data to optical beams for on-chip movements with waveguides and computations with optical devices. Without capacitive resistance in optical waveguides, memory no longer needs to be physically close to processors, enabling potentially unlimited memory capacities.
Photonic devices are significantly larger than electronic transistors, which makes scaling existing optical computing approaches that map neural parameters onto photonic hardware (1 device/parameter) challenging. Opticore addresses this limitation by leveraging innovations in temporal mapping, where neural data is encoded using optical pulses. For example, an optical modulator can activate tens of billions of parameters per second, and through parallel channels, trillions of parameters can be processed simultaneously. Furthermore, all parameters can be dynamically programmed for training tasks, enabling highly flexible and scalable computing.
The Opticore computing chips are fabricated with standard foundry services, with co-packed optolelectronics and hyperbonding of HBMs.
- MIT news
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